1. Field of the Invention
The present invention generally relates to the integrated circuit and circuit board design fields and more specifically to connection of components through use of buses in integrated circuits and circuit boards.
2. Description of the Related Art
As technology advances, and new products with advanced features appear, the need for backward compatibility and interoperability surfaces as a constraint in the design of prospective products. As an example, newer computers are expected to be capable of running software that predates the conception of the newer computers.
Prior art systems often use a configuration of components as illustrated in FIG. 1. CPU 101 (a Central Processor or Processor) is coupled through a Processor Bus 102 to a component referred to as a Host Bridge 105, and thereby coupled to the rest of the system. Host Bridge 105 is coupled to Memory 103, the main memory of the system, and Host Bridge 105 is also coupled to I/O Bridge 107 (Input/Output Bridge). I/O Bridge 107 couples to Keyboard 109, Mouse 111, and Disk Drive 110, and may couple to other components in a bus or point-to-point fashion. Through these couplings, CPU 101 is coupled to each component in the system, and may read or write information to each of the devices (within the capabilities of those devices).
Further extending the complexity of the system, PCI Bus 125 (Peripheral Component Interconnect Bus based on the Peripheral Component Interconnect Bus Specification Revision 2.1 or 2.2 from the Portland PCI Working Group as published by Intel Corporation) may be involved in the coupling of Host Bridge 105 to I/O Bridge 107, and may thereby couple to PCI Agents 120. Thus, through Host Bridge 105, CPU 101 may communicate with PCI Agents 120. While it is advantageous to make PCI Agents 120 available to the system, incorporating the PCI Bus 125 into a coupling or connection between the Host Bridge 105 and the I/O Bridge 107 further complicates the physical devices and layout, and the protocols for communication over that coupling.
FIG. 1B provides a simplified illustration of a subsystem from the system of FIG. 1A. FIG. 1B includes Host Bridge 105, I/O Bridge 107, and PCI Agents 120. Connected to each of these three components are A/D lines 195, PHLD (P Hold) 196, PHLD_ACK (P Hold Acknowledge) 197 and SERR# 198. PHLD 196, PHLD_ACK 197, and SERR 198 are signals well known in the implementation of the PCI Bus. All of A/D 195, PHLD 196, PHLD_ACK 197 and SERR# 198 are incorporated in PCI Bus 125 of is FIG. 1A, along with other signals not shown.
In the case of an upstream data transfer, one function of PHLD 196 and PHLD_ACK 197 is to arbitrate between components on the PCI bus. PHLD 196 is asserted by the I/O Bridge or whatever component is connected to it when that component will be transferring data upstream. In some embodiments, to ensure that the data transferred upstream will be correct, all pending downstream writes, such as data pending in the Host Bridge 105 which needs to be written downstream, must be written. Otherwise, data transferred upstream may be incorrect because a pending write was intended to modify that data. So, upon receiving PHLD 196, Host Bridge 105 will, in one embodiment, complete all downstream write transactions. Upon completion of those write transactions, Host Bridge 105 will assert PHLD_ACK 197, indicating Host Bridge 105 has received the PHLD 196 signal and is prepared for the upstream data transfer.
In other embodiments, the device asserting PHLD 196 may be capable of being the master of a bus other than the PCI Bus (such as an EISA bus) for an indefinite amount of time. In those instances, the device must also effectively be given control of the PCI Bus, so control of the PCI Bus is transferred when PHLD_ACK 197 is asserted, and control is not relinquished until PHLD 196 is deasserted.
SERR# 198 is a system error signal, which may be asserted by a pulse, rather than a steady high or low logic level. SERR# 198 is asserted in the case of errors associated with a transaction or an agent on the PCI Bus. As will be appreciated, most busses are more complicated than that illustrated in FIG. 1B, including the PCI Bus, which often uses at least six separate control signals, rather than the three illustrated.
It will be appreciated that many other signals may be incorporated into buses as separate pins on each component or wires connecting the components. Such signals may have assertion/de-assertion characteristics similar to PHLD 196 for example, or may be used in a pulsed manner more like SERR# 198, where any change in state either synchronous or asynchronous must be handled by the components. As these signals increase in number, routing of signals on an integrated circuit die or a circuit board becomes more complex, the number of pins and bond pads on individual integrated circuits may increase, and costs will correspondingly increase for both design and manufacture.